Earlier methods for forming FDSOI devices rely on abundant placement of back gates and well taps that result in overhead loss to chip density. The size of the contacts are determined by opening the SOI to expose bulk silicon, which must be disposed at a distance away from active FDSOI gates. This distance diminishes active area efficiency, thereby increasing minimum chip size.
A need exists for methodology enabling minimization of a space between a well contact and an active FDSOI gate and the resulting device.